The present invention relates to a slip phase control phase-locked loop for generating a frequency-controlled output signal.
Analog and digital phase-locked loops (PLL) are widely used as highly-accurate frequency-controlled oscillators in radio communication systems or the like.
One example of a PLL capable of producing an output signal having a high C/N (carrier signal/noise) ratio is a slip phase control PLL disclosed in Japanese Laid-Open Patent Publication No. 63(1988)-26589.
The disclosed slip phase control PLL has a voltage-controlled oscillator (VCO), a phase comparator, a low-pass filter (LPF), and a programmable frequency divider which comprises a pulse-swallow-type 2-scale-factor prescaler, a swallow counter, and a main counter.
The slip phase control PLL also includes a sawtooth generator for dividing a variable division ratio by (n+q) (q is an integer other than 0) in each period T and generating a sawtooth wave having a period T. The output signal of the sawtooth generator is added or subtracted by the low-pass filter so that a slip phase waveform of the output signal from the phase comparator will be canceled out.
With the above arrangement, since no ripples are produced in a control voltage, particularly a low voltage, applied to the variable capacitor or the like of the VCO, the noise figure (NF) of the VCO is increased, and the VCO can produce an output signal of a high C/N ratio.
In the programmable frequency divider, when the 2-scale-factor prescaler has division ratios of 2.sup.M and 2.sup.M +1, the swallow counter counts m pulses according to a preset number m, and the main counter divides the input frequency by n according to a preset number n. During an m-counting period in which n pulses are being counted by the main counter, the 2-scale-factor prescaler divides the input frequency by 2.sup.M +1, and during the remaining (n-m)-counting period, the 2-scale-factor prescaler divides the input frequency by 2.sup.M.
The total division ratio q of the programmable frequency divider is given by: EQU q=m.times.(2.sup.M +1)+(n-m).times.2.sup.M =m+2.sup.M .times.n (1)
The slip phase control PLL can control an oscillation frequency highly accurately, but is relatively complex in arrangement.
The preset number m varies from 0 to 2.sup.M -1 in order to generate a signal to be supplied to the LPF for canceling out the slip phase waveform. Based on this fact, efforts to reduce the circuit scale are directed to the addition of a D/A converter which counts output pulses of the 2-scale-factor prescaler during an interval in which the division ratio of the 2-scale-factor prescaler is of a constant value of 2.sup.M.
However, the D/A converter has a D/A conversion range which is limited to a pulse count that ranges from 0 to n-2.sup.M, and hence cannot achieve a multiple-frequency output capability. The above drawbacks should be eliminated in view of demands for highly accurate frequency control, reduced circuit scales, and a reduced number of signal processing cycles.